1. Field of the Invention
The present invention relates to liquid crystal displays (LCDs). More particularly, the present invention relates to an apparatus and method for driving LCDs that minimizes the generation of electro-magnetic interference (EMI) in a cost efficient manner.
2. Discussion of the Related Art
Generally, LCDs display pictures by controlling light transmittance characteristics of liquid crystal cells in accordance with received video signals. Active matrix type LCDs include switching devices (usually a thin film transistor (TFT)) coupled to liquid crystal cells. Such active matrix type LCDs are often used as monitors for computers, office equipment, cellular phones, and the like.
FIG. 1 illustrates a related art LCD driving apparatus.
Referring to FIG. 1, the related art LCD driving apparatus includes an LCD panel 2 having m×n liquid crystal cells Clc arranged in a matrix pattern, m data lines D1 to Dm, n gate lines G1 to Gn crossing the m data lines D1 to Dm, TFTs provided at the crossings of the data and gate lines, a data driver 4 for applying data signals to the data lines D1 to Dm, a gate driver 6 for applying scanning signals to the gate lines G1 to Gn, a gamma voltage supplier 8 for supplying the data driver 4 with gamma voltages, a timing controller 10 for controlling the data driver 4 and the gate driver 6 using synchronizing signals outputted from a system 20, a direct current to direct current (DC/DC) converter 14 for generating voltages supplied to the LCD panel 2 using a voltage outputted from a power supply 12, an inverter 16 for driving a back light 18, and a filter array 22 for minimizing the generation of electro-magnetic interference (EMI).
The system 20 outputs vertical signals Vsync, horizontal signals Hsync, clock signals DCLK, a data enable signal DE, and R, G and B data to the timing controller 10.
The LCD panel 2 includes a plurality of liquid crystal cells Clc arranged in a matrix pattern at the crossings of the plurality of data lines D1 to Dm and the plurality of gate lines G1 to Gn. TFTs are provided at each liquid crystal cell Clc to apply data signals, transmitted by the data lines D1 to Dm, to corresponding liquid crystal cells Clc in response to scanning signals transmitted by gate lines G1 to Gn. Further, a storage capacitor Cst is provided either between a pixel electrode of each liquid crystal cell Clc and a pre-stage gate line or between the pixel electrode of each liquid crystal cell Clc and a common electrode line. The storage capacitor Cst functions to maintain a voltage charged within the liquid crystal cell Clc.
The gamma voltage supplier 8 applies a plurality of gamma voltages to the data driver 4.
The data driver 4 converts digital R, G and B video data into analog gamma voltages (i.e., data signals) having predetermined gray level values and applies the data signals to the data lines D1 to Dm in response to data control signals DCS outputted from the timing controller 10.
The gate driver 6 sequentially applies scanning pulses to the gate lines G1 to Gn in response to a gate control signal GCS outputted from the timing controller 10. Accordingly, the gate driver 6 selects horizontal lines of liquid crystal cells Clc within the LCD panel 2 that are supplied with data signals.
The DC/DC converter 14 generates a supply voltage for the LCD panel 2 by either boosting or dropping a voltage of 3.3V outputted from the power supply 12. The DC/DC converter 14 also generates a gamma reference voltage, a gate high voltage VGH, a gate low voltage VGL, a common voltage Vcom, etc.
The inverter 16 drives the backlight 18 by applying a driving voltage (or driving current) thereto. Upon receipt of the driving voltage (or driving current), the backlight 18 emits light to the LCD panel 2.
Using the vertical/horizontal synchronizing signals Vsync and Hsync and the clock signal DCLK outputted from the system 20, the timing controller 10 generates the gate and data control signals GCS and DCS, respectively, for controlling the gate and data drivers 6 and 4, respectively.
To this end, and with reference to FIG. 2, the related art timing controller 10 includes a gate control signal generator 30 for generating the gate control signals GCS which, in turn, control the gate driver 6, a data control signal generator 32 for generating the data control signals DCS which, in turn, control the data driver 4, a data aligner 34 for re-aligning the R, G and B data outputted by the system 20 and for applying the re-aligned R, G, and B data to the data driver 4, and a control unit 33 for controlling the gate signal generator 30, the data control signal generator 32, and the data aligner 34. Specifically, the control unit 33 controls the gate control signal generator 30 to generate gate control signals GCS (i.e., gate start pulse GSP, gate shift clock GCS, and gate output enable signal GOE), controls the data control signal generator 32 to generate data control signals DCS (i.e., source start pulse SSP, source shift clock SSC, source output enable signal SOE, and polarity signal POL); and controls the data aligner 34 to re-align externally inputted R, G and B data.
First, second, and third buffers 36, 37, and 38, respectively, are provided at respective outputs of the gate control signal generator 30, the data control signal generator 32, and the data aligner 34.
The first buffer 36 ensures that the current value of gate control signals GCS outputted from the gate control signal generator 30 are maintained at a predetermined value. Similarly, the second buffer 37 ensures that the current value of the data control signals DCS outputted from the data control signal generator 32 are maintained at a predetermined value. The predetermined current values of the gate and data control signals GCS and DCS are values sufficient to ensure that the gate and data control signals GCS and DCS are suitably applied to each integrated circuit within the gate and data drivers 6 and 4, respectively. The third buffer 38 ensures that the current value of the R, G and B data outputted from the data aligner 34 are maintained at a predetermined value, facilitating stable outputting of data.
The filter array 22 is provided between the timing controller 10 and the data and gate drivers 4 and 6, respectively, and controls waveforms of the gate control signal GCS, the data control signal DCS, and the R, G and B data outputted from the timing controller 10 to minimize the generation of electro-magnetic interference (EMI). To this end, the related art filter array 22 includes a first filter 22a connected to the first buffer 36 to filter waveforms of the gate control signals GCS, a second filter 22b connected to the second buffer 37 to filter waveforms of the data control signals DCS, and a third filter 22c connected to the third buffer 38 to filter waveforms of the R, G, and B data.
With specific reference to FIG. 3, the various signals outputted to the first, second, and third filters 22a, 22b, and 22c are characterized as having rectangular waveforms. After being filtered by the first to third filters 22a-c, however, the various signals are characterized as having sloped waveforms, experimentally determined to beneficially minimize the generation of electro-magnetic interference (EMI).
Use of the aforementioned related art LCD including the filter array 22 however, is disadvantageous because it can be very expensive to manufacture. Further, if the filter array 22 is mounted onto a printed circuit board (PCB), then design flexibility of the PCB may become unduly limited.